1. Field of the Invention
The present invention relates to a test method and a test circuit, and more particularly, to a method for testing a through-silicon-via and the circuit thereof.
2. Description of the Related Art
Three-dimensional integrated circuit (3D IC) technology, a promising technology in the field of modern electronics, is a technology in which two or more layers of active electronic components are integrated into a chip. In other words, a 3D IC packages a plurality of ICs into a single chip. Compared with a traditional single IC chip, a 3D IC provides a faster signal transmission rate between ICs, generates less noise, consumes less power, occupies less space and produces better performance.
Recent research and development in 3D IC technology has emphasized the benefit of increased packing density attainable by stacking a growing number of ICs. In addition, 3D IC technology offers an opportunity to integrate heterogeneous processes in a more efficient manner, improves speed performance with smaller interconnect delays, decreases power consumption with shorter wire lengths and increases data bandwidth by using short vertical links or vertical interconnection between dies known as through-silicon-via (TSV). According to the step of TSV formation in an overall 3D IC manufacturing sequence, we could classify TSV technologies into two main categories, namely, via-first and via-last. One categorization is to separate by the bonding step. The via-first processes form the TSVs on each wafer prior to the bonding step, and the via-last processes form the TSVs after. Compared with other alternatives for linking the plurality of ICs, such as wire bonding and micro-bumping, TSVs achieve higher interconnection density and better performance.
In spite of the advantages mentioned above, there are some problems associated with 3D IC technology. One of the most important issues is the compound yield loss due to IC stacking. To guarantee the stacking yield, the interconnection must be tested. The current interconnection test proposed for 3D IC is done with two or more dies in a stack, which is good only for TSVs after bonding. Essentially, after two dies are bonded, the TSVs can be connected serially to form a daisy chain in an electric test or connected with flip-flops to form a scan chain in a structure test. There needs high reliability TSV channels for test control or scan path. With the same test circuit in each layer, they can be tested in a complete or partial stack.
However, there are some limitations in these test schemes. First, they cannot be performed before bonding. A straightforward way for an electric test uses a daisy chain structure of by alternate routes of TSVs on both the front and back sides of the wafer. Apparently, this scheme is suitable only for the wafer acceptance test (WAT), since it is extremely difficult, if not impossible, to dismantle and rework the back metal once the TSV test is done. As a result, the observation of TSV failures at this stage relies solely on a couple of test keys on the scribe line. Second, individual TSVs are indistinguishable in a serial scan chain or a daisy chain, so diagnosis becomes an issue. Probing both ends of a TSV can measure its resistance as the pass/fail criterion, but the area overhead for direct access is high, and thus is limited to a small number of sparse TSVs. Also, in general, for a die before bonding, the TSVs have one end on the backside that is not only floating but also buried deeply in the wafer substrate before thinning. Third, in the case of a via-first process, which intend to provide an interconnection density as high as 104/mm2, on-chip TSV monitoring becomes necessary. However, there are not always flip-flops connected to both ends of each TSV. In addition, the TSV failure rate affects the final yield exponentially with the number of dies in a stack. Unfortunately, it remains relatively high (>10 ppm). Without screening out the bad ones, the overall yield of the die stack will be low.
In view of the above, it is necessary to design a test method, which not only can be performed on TSVs before bonding, but also allows each TSV to be tested individually.